The present invention relates to a method for designing a cell array layout of a non-volatile memory device. More particularly, it relates to a method for designing a cell array layout of a non-volatile memory device, which facilitates formation of a contact hole and reduction of chip size by modifying the layout of an active contact hole for applying a voltage to the cell array.
A memory device for storing data has a great significance in a data processing system. Semiconductor, memory devices are largely grouped into volatile memory devices whose information is destroyed when power is interrupted and non-volatile memory devices whose information is retained despite the interruption of power. The non-volatile memory can be further categorized into two types: a read only memory (ROM) in which only the read-operation of input data can be performed, and an electrically erasable and programmable read only memory (EEPROM) in which input data can be electrically erased as well as entered. As a type of EEPROM, there is the flash EEPROM whose contents can be erased simultaneously.
Non-volatile memory generally employs a floating gate electrode and a control gate electrode, together. In this type of non-volatile memory, a floating gate is formed of a conductive material electrically insulated from the semiconductor substrate. The floating gate functions as a MOS transistor which senses the charge state. The storage of 1 or 0 is, therefore, determined by the presence or absence of charge in the floating gate. Injecting and removing charge into and from the floating gate relies on hot electrons generated by avalanche breakdown and F-N(Fowler Nordheim) tunneling effects.
FIG. 1 is a simplified view of a conventional cell array of a non-volatile memory device.
In FIG. 1 the string select transistor lines SSL1 and SSL2, and ground select transistor lines GSL1 and GSL2 are arranged in a predetermined direction (horizontally) in the upper and lower parts, respectively, and word lines W/L1-W/L.sub.n are arranged in parallel with select transistor lines SSL1, SSL2, GSL1 and GSL2. Memory cells having floating gates are connected in series between select transistor lines SSL1 and GSL1, constituting a string. Bit lines B/L1-B/L3 are arranged orthogonal to word lines W/L1-W/L.sub.n and connected to string select transistor lines SSL1 and SSL2 through bit line contact holes 1. A common source line C/S and common source contact holes 5 are arranged between ground select transistor lines GSL1 and GSL2.
When programming a cell 7 of the conventional nonvolatile memory device, a program voltage Vpgm of approximately 20V is applied to a control gate of cell 7 and a passing voltage Vpass of about 10V is applied to the control gates of the other unselected cells. This keeps the unselected cells connected to the control gate of the selected cell from being programmed. In other words, 0V is applied to bit line, (i.e. data line) B/L2 of a cell string having selected cell 7, a voltage Vcc to the other bit lines B/L1 and B/L3, a voltage Vpgm of about 20V to control gate W/Ln to which cell 7 belongs, a voltage Vpass of about 10V to the other unselected control gates W/L1-W/L.sub.n-1, and a ground voltage or a voltage Vcc to the common source line C/S.
A conventional method for designing a memory cell array layout will now be described.
FIGS. 2, 3 and 4 are views for explaining the conventional method for designing a cell array layout of a non-volatile memory device. FIG. 2 is a conventional cell array layout view of the non-volatile memory device, FIG. 3 is a cross-sectional view along line a-a1 of FIG. 2, and FIG. 4 is a cross-sectional view along line b-b1 of FIG. 2.
As shown in FIGS. 2, 3 and 4, in the conventional cell, array layout of the non-volatile memory device, string select transistor lines SSL1 and SSL2, and ground select transistor lines GSL1 and GSL2 are arranged in a predetermined direction (horizontally) in the upper and lower parts, respectively. Word lines W/L1-W/L.sub.n and floating gates 9 are arranged in parallel with select transistor lines SSL1, SSL2, GSL1 and GSL2. Bit line contact holes 11 are arranged between select transistor lines SSL1 and SSL2, active source line 13 is arranged parallel to word lines W/L1-W/L.sub.n, and active lines 15 are arranged orthogonal to active source line 13. A common source contact hole 17 is provided between regular cell strings, and connected to active lines 15.
A conventional NAND memory cell having a floating gate and a control gate needs common source contact hole 17 for applying a voltage to the substrate in which the cell array is placed. Common source contact hole 17, which is formed at the start of another cell string following a repetition of regular cell strings, exhibits the following problems in applications of the non-volatile memory device.
First, the growth speed of an oxide film increases in the oxidation of a large area of silicon rather than a relatively small area of silicon. Therefore, field oxide film 19 formed over a large area becomes thicker than another field oxide film 20 formed between adjacent cell strings, as shown in FIG. 3. Ground select transistor 29 constituted by floating gate 21, a dielectric film 23, and word line 25 is formed on field oxide film 19, thereby increasing the contact hole aspect ratio. Under this situation, the distance between word lines 25 must be maintained to be tl, as shown in FIG. 4. Thus, the conventional layout designing method imposes limitations upon reducing chip size.
As shown in FIGS. 2, 3 and 4, active lines 15 having common source contact hole 17 therebetween are formed apart from each other at a predetermined distance. When active-etching for defining an active region and a non-active region in a local oxidation of silicon (LOCOS) process, the etch rate difference caused by a microloading effect makes the width of silicon nitride films of both the cell strings spaced by common source contact hole 17 wider than those of adjacent cell strings. Namely, W.sub.2 and W.sub.3 are larger than W.sub.1 and W.sub.4 as shown in FIG. 3. This microloading effect also makes the width of active regions in cells formed in active lines adjacent to field oxide film 19 larger than that of the active regions in the cells formed in any other active line, thereby producing different coupling ratios. As a result, there is a high probability of programming failures.